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PART NUMBER:
± 2g / 4g / 8g Tri-axis Digital
Accelerometer Specifications
KXTF9-4100
Rev. 6
Jun-2011
TDT_TAP_TIMER
This register contains counter information for the detection of any tap event. Every count is calculated
as 1/ODR delay period, where the ODR is user-defined per Table 17. In order to ensure that only tap
events are detected, these time limits are used. A tap event must be above the performance index
threshold (TDT_THRESH) for at least the low limit (FTDL0 – FTDL2) and no more than the high limit
(FTDH0 – FTDH4). The Kionix recommended default value for the high limit is 0.05 seconds and for
the low limit is 0.005 seconds (0xA2h). Note that to properly change the value of this register, the PC1
bit in CTRL_REG1 must first be set to “0”.
R/W
FTDH4
Bit7
R/W
FTDH3
Bit6
R/W
FTDH2
Bit5
R/W
FTDH1
Bit4
R/W
FTDH0
Bit3
R/W
FTDL2
Bit2
R/W
FTDL1
Bit1
R/W
FTDL0
Bit0
Reset Value
10100010
I C Address: 0x2Eh
2
TDT_TOTAL_TIMER
This register contains counter information for the detection of a double tap event. Every count is
calculated as 1/ODR delay period, where the ODR is user-defined per Table 17. In order to ensure
that only tap events are detected, this time limit is used. This register sets the total amount of time that
the two taps in a double tap event can be above the PI threshold (TDT_L_THRESH). The Kionix
recommended default value for TDT_TOTAL_TIMER is 0.09 seconds (0x24h). Note that to properly
change the v alue of this register, the PC1 bit in CTRL_REG1 must first be set to “0”.
R/W
STD7
Bit7
R/W
STD6
Bit6
R/W
STD5
Bit5
R/W
STD4
Bit4
R/W
STD3
Bit3
R/W
STD2
Bit2
R/W
STD1
Bit1
R/W
STD0
Bit0
Reset Value
00100100
I C Address: 0x2Fh
2
36 Thornwood Dr. – Ithaca, NY 14850
tel: 607-257-1080 – fax:607-257-1146
www.kionix.com - info@kionix.com
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